Frequency jittering control circuit and method for a pfm power supply

ABSTRACT

A frequency jittering control circuit for a PFM power supply includes a pulse frequency modulator to generate a frequency jittering control signal to switch a power switch to generate an output voltage. The frequency jittering control circuit jitters an input signal or an on-time or off-time of the pulse frequency modulator to jitter the switching frequency of the power switch to thereby improve EMI issue.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a Continuation of U.S. patent applicationSer. No. 13/567,272, filed 6 Aug. 2012, which claims priority to TaiwanPatent Application No. 100130691, filed 26 Aug. 2011, and all thebenefits accruing therefrom under 35 U.S.C. §119, the contents of whichin its entirety are herein incorporated by reference.

FIELD OF THE INVENTION

The present invention is related generally to a switching mode powersupply (SMPS) and, more particularly, to pulse frequency modulation(PFM) power supply.

BACKGROUND OF THE INVENTION

Electro-magnetic interference (EMI) is known as a critical issue indesigning a switching power supply, and is typically improved byspread-spectrum approaches that improve EMI by jittering the switchingfrequency of the power supply. Existing pulse width modulation (PWM)power supply devices, as those disclosed in U.S. Pat. Nos. 5,929,620,6,249,876 and 7,289,582, mainly accomplish spectrum-spreading byjittering the frequency of the oscillator and in turn jittering theswitching frequency of the power supply. A PFM power supply is avariable-frequency system whose switching frequency varies with itsload, so is less subject to EMI. Such a PFM power supply, however, whenhaving a consistent load, has its switching frequency held consistent,and thus still suffers from EMI. Nevertheless, it is infeasible in thePFM power supply to jitter the switching frequency by jittering thefrequency of an oscillator that is absent.

SUMMARY OF THE INVENTION

An objective of the present invention is to provide a frequencyjittering control circuit and method for a PFM power supply.

According to the present invention, a frequency jittering controlcircuit for a PFM power supply comprises a pulse frequency modulator forgenerating a frequency jittering control signal to switch a power switchand generate an output voltage. In a peak-current mode PFM power supply,the pulse frequency modulator turns on the power switch by triggeringthe control signal responsive to a first signal, and turns off the powerswitch by terminating the control signal responsive to a second signal.The frequency jittering control circuit jitters the first or secondsignal to generate the frequency jittering control signal. In a quasiresonant mode PFM power supply, the pulse frequency modulator jittersthe on or off time in order to generate the frequency jittering controlsignal. In a constant-on-time mode or constant-off-time mode PFM powersupply, the pulse frequency modulator jitters the constant on-time orconstant off-time in order to generate the frequency jittering controlsignal.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objectives, features and advantages of the presentinvention will become apparent to those skilled in the art uponconsideration of the following description of the preferred embodimentsaccording to the present invention taken in conjunction with theaccompanying drawings, in which:

FIG. 1 is a circuit diagram of a first embodiment according to thepresent invention;

FIG. 2 is a waveform diagram of the control signal for switching thepower switch shown in FIG. 1;

FIG. 3 is a circuit diagram of a first embodiment for the signalgenerator shown in FIG. 1;

FIG. 4 is a circuit diagram of a second embodiment for the signalgenerator shown in FIG. 1;

FIG. 5 is a circuit diagram of a second embodiment according to thepresent invention;

FIG. 6 is a circuit diagram of a third embodiment according to thepresent invention;

FIG. 7 is a circuit diagram of a fourth embodiment according to thepresent invention;

FIG. 8 is a circuit diagram of a fifth embodiment according to thepresent invention;

FIG. 9 is a circuit diagram of a sixth embodiment according to thepresent invention;

FIG. 10 is a circuit diagram of a seventh embodiment according to thepresent invention;

FIG. 11 is a circuit diagram of an eighth embodiment according to thepresent invention;

FIG. 12 is a circuit diagram of a ninth embodiment according to thepresent invention;

FIG. 13 is a circuit diagram of a tenth embodiment according to thepresent invention;

FIG. 14 is a circuit diagram of an eleventh embodiment according to thepresent invention; and

FIG. 15 is a circuit diagram of an embodiment for the constant timegenerator shown in FIG. 14.

DETAILED DESCRIPTION OF THE INVENTION

A first embodiment according to the present invention shown in FIG. 1 isa peak-current mode PFM power supply that comprises a transformer 10, apower switch M1 connected in series to a primary coil Lp of thetransformer 10, and a frequency jittering control circuit that generatesa frequency jittering control signal Vg for switching the power switchM1, thereby converting an input voltage Vin into an output voltage Vo.In the frequency jittering control circuit, there are a pulse frequencymodulator 12 for generating the control signal Vg according to a firstsignal S1 and a second signal S2, a current detector 14 for detecting acurrent Ip of the power switch M1 to generate a current sense signalVcs, an output voltage feedback circuit 16 for detecting the outputvoltage Vo to generate a feedback signal VFB, a comparator 20 forcomparing the feedback signal VFB with a reference voltage Vref togenerate the first signal S1, a signal generator 18 for providing ajittering signal VL, and a comparator 22 for comparing the signal VLwith the current sense signal Vcs to generate the second signal S2. Inthis embodiment, the current detector 14 comprises a current sensingresistor Rcs connected in series to the power switch M1, for generatingthe current sense signal Vcs when the current Ip passes therethrough.The pulse frequency modulator 12 comprises a flip-flop 24 for generatinga pulse frequency modulating signal Q responsive to the signals S1 andS2, and a gate driver 26 for generating the control signal Vg responsiveto the pulse frequency modulating signal Q. In the pulse frequencymodulator 12, the signals S1 and S2 are input to a setting terminal Sand a resetting terminal R of the flip-flop 24, respectively, so thepulse frequency modulating signal Q is to be triggered by the firstsignal S1 and terminated by the second signal S2, thereby controllingthe on time of the power switch M1 to start and end, and in turncontrolling the on-time of the power switch M1. More particularly,whenever the output voltage Vo decreases to become lower than thereference voltage Vref, the first signal S1 turns to be logic “1”,thereby triggering the pulse frequency modulating signal Q, and in turnturning on the power switch M1 to make the current Ip increase. When thecurrent sense signal Vcs increases to become higher than the signal VL,the second signal S2 turns to be logic “1”, thereby resetting the signalQ, and in turn turning off the power switch M1. Since the signal VLjitters, the time for the signal Q to be turned off jitters to jitterthe switching frequency of the power switch M1. FIG. 2 illustrates theprocess clearly. With the rising slope of the current sense signal Vcsremaining unchanged, when the signal VL increases from VL1 to VL2, thecurrent sense signal Vcs needs more time to rise to the signal VL. Thus,the cycle of the control signal Vg increases from T1=1/f1 to T2=1/f2, asshown by waveforms 28 and 29, respectively, meaning that the switchingfrequency of the power switch M1 decreases from f1 to f2. On thecontrary, when the signal VL decreases, the switching frequency of thepower switch M1 increases. Therefore, jittering the signal VL is aneffective way to jitter the switching frequency of the power switch M1,in turn improving the EMI problem in the PFM power supply.

FIG. 3 is a first embodiment of the signal generator 18 of FIG. 1. Inthe left part, a voltage-to-current converter 30 and a current mirror 32are for generating the preset signal VL, while a counter 34, a rampgenerator 36, a voltage-to-current converter 38 and a current mirror 40in the right part of FIG. 3 are for jittering the signal VL. Thevoltage-to-current converter 30 converts the reference voltage Vref1into a current I1. The current mirror 32 mirrors the current I1 togenerate a current I2. The ramp generator 36 provides a ramp signal Vra.The counter 34 generates a count value CNT according to a clock CLK forthe ramp generator 36 to adjust the ramp signal Vra. Thevoltage-to-current converter 38 converts the ramp signal Vra into acurrent I3. The current mirror 40 mirrors the current I3 to generate acurrent I4. The currents I2 and I4 are combined into a jittering currentI5, which passes through a resistor Ro to generate the jittering signalVL. The clock CLK may be generated by a periodic signal in the PFM powersupply, such as the signal Q, Vg or VFB. In other embodiments, thecounter 34 may be replaced by a different circuit, such as a randomnumber generator.

FIG. 4 is a second embodiment of the signal generator 18 of FIG. 1, withthe left part identical to that in FIG. 3. The rest of the circuit iscomposed of a variable resistor 42 and a resistance controller 44. Thevariable resistor 42 includes a resistor Radj and the resistor Roconnected in series. The resistance controller 44 finely adjusts theresistor Radj to change the resistance of the variable resistor 42,thereby jittering the signal VL. The resistance controller 44 may berealized by a counter or a random number generator.

The embodiment shown in FIG. 1 jitters the switching frequency byjittering the second signal S2, but the other embodiment can jitter theswitching frequency by jittering the first signal S1. As the embodimentshown in FIG. 5, the first signal S1 is delayed by a programmable delaycircuit 46 for a period of time before it is sent to the pulse frequencymodulator 12. A delay time controller 48 adjusts the delay time of theprogrammable delay circuit 46 according to the output Q of the flip-flop24, thereby jittering the time where the signal Q is triggered, and inturn, jittering the switching frequency of the power switch M1. Thedelay time controller 48 may be realized by a counter or a random numbergenerator. In other embodiments, the delay time controller 48 may adjustthe delay time of the programmable delay circuit 46 alternativelyaccording to another periodic signal, such as the signal Vg or VFB.

The jitter approach of FIG. 5 may be modified into the embodiment shownin FIG. 6, where the second signal S2 is delayed by the programmabledelay circuit 46 for a period of time before sent into the pulsefrequency modulator 12, and the delay time controller 48 adjusts thedelay time of the programmable delay circuit 46 according to the outputQ of the flip-flop 24, thereby jittering the time where the signal Q isreset, and in turn jittering the switching frequency of the power switchM1.

While the embodiment of FIG. 1 jitters the second signal S2 by means ofjittering the signal VL, it is also feasible to jitter the second signalS2 by jittering the current sense signal Vcs. As the embodiment shown inFIG. 7, the current sense signal Vcs is amplified by a gain circuit 50into a signal Vcs_m. A gain controller 52 adjusts a gain Ki of the gaincircuit 50 according to the control signal Vg, thereby changing therising slope of the current sense signal Vcs_m, and in turn changing thetime where the second signal S2 is triggered, so as to finally changethe time where the signal Q is terminated. When the gain Ki of the gaincircuit 50 jitters, the switching frequency of the power switch M1jitters accordingly. In other embodiments, the gain controller 52 mayadjust the gain Ki according to another periodic signal. The gaincontroller 52 may be realized by a counter or a random number generator.

FIG. 8 is a quasi resonant (QR) mode PFM power supply, which includes azero current detector 54 for detecting an output current Io of the PFMpower supply and triggering the first signal S1 for the pulse frequencymodulator 12 when the output current Io decreases and reaches athreshold value. The current detector 14 detects the current Ip of thepower switch M1 to generate the current sense signal Vcs. The outputvoltage feedback circuit 16 detects the output voltage Vo to generatethe feedback signal VFB. An error amplifier 55 amplifies the differencebetween the feedback signal VFB and the reference voltage Vref togenerate a third signal S3. The comparator 22 compares the current sensesignal Vcs with the third signal S3 to generate the second signal S2.The pulse frequency modulator 12, similar to the embodiment of FIG. 1,has the signal Q triggered by the first signal S1 and reset by thesecond signal S2. For jittering the second signal S2, the programmabledelay circuit 46 delays the second signal S2 for a period of time beforesending it to the pulse frequency modulator 12. The delay timecontroller 48 adjusts the delay time of the programmable delay circuit46 according to the control signal Vg. Jittering the delay time of theprogrammable delay circuit 46 jitters the time where the signal Q isterminated, thereby jittering the switching frequency of the powerswitch M1.

The approach to jittering the second signal S2 as shown in FIG. 8 may bemodified into the embodiment of FIG. 9, where the gain circuit 50amplifies the current sense signal Vcs into Vcs_m, and the gaincontroller 52 jitters the gain Ki of the gain circuit 50 according tothe control signal Vg, thereby jittering the rising slope of the currentsense signal Vcs_m, then jittering the time where the second signal S2is triggered, and in turn jittering the time where the signal Q isterminated, so as to finally jitter the switching frequency of the powerswitch M1.

The method for jittering the rising slope of the current sense signalVcs_m as shown in FIG. 9 may be modified into the embodiment of FIG. 10,where the gain circuit 50 amplifies the feedback signal VFB into VFB_m,and the gain controller 52 jitters the gain Ki of the gain circuit 50according to the control signal Vg, thereby jittering the rising slopeof the feedback signal VFB_m, in turn jittering the time where thesecond signal S2 is triggered, so as to jitter the time when the signalQ is terminated and finally make the switching frequency of the powerswitch M1 jitter accordingly.

The embodiments of FIGS. 8-10 all involve comparing the current sensesignal Vcs related to the current Ip of the power switch M1 with thethird signal S3 to generate the second signal S2. In other embodiments,another ramp signal may be implemented to replace the current sensesignal Vcs. For example, the circuit of FIG. 8 may be modified into a QRvoltage mode PFM power supply as shown in FIG. 11. Therein thecomparator 22 compares the internal ramp signal Vramp with the thirdsignal S3 to generate the second signal S2. The circuit of FIG. 9 may bemodified into a voltage mode structure as shown in FIG. 12. Therein thegain circuit 50 amplifies a ramp signal Vramp to generate a ramp signalVramp_m, and the comparator 22 compares the ramp signal Vramp_m with thethird signal S3 to generate the second signal S2. The circuit of FIG. 10may be modified into a voltage mode structure as shown in FIG. 13.Therein, the comparator 22 compares the ramp signal Vramp with the thirdsignal S3 to generate the second signal S2.

The embodiment shown in FIG. 14 is a constant on-time or constantoff-time mode PFM power supply. Its pulse frequency modulator 12comprises a one-shot circuit 56 triggered by the first signal S1 togenerate a pulse signal S4 whose pulse width is determined by theconstant time Ton from a constant time generator 58. The constant timeTon is finely adjusted by the constant time adjuster 60 according to thecontrol signal Vg so as to become jittering. The gate driver 26generates the control signal Vg responsive to the pulse signal S4. Byjittering the length of the constant time Ton, the on time or off timeof the power switch M1 is jittered, thereby jittering the switchingfrequency of the power switch M1. In other embodiments, the constanttime adjuster 60 may jitter the length of the constant time Tonalternatively according to another periodic signal, such as the feedbacksignal VFB. The constant time adjuster 60 may be realized by a counteror a random number generator.

FIG. 15 is one embodiment of the constant time generator 58 of FIG. 14,which includes a current source 62 for providing a charging current Icthat charges a capacitor Cv to generate a charging voltage Vc, acomparator 64 for comparing the charging voltage Vc with a thresholdvoltage Vb provided by a voltage source 66 to determine the length ofthe constant time Ton. The constant time adjuster 60 adjusts at leastone of the capacitor Cv, the charging current Ic and the thresholdvoltage Vb, thereby jittering the length of the constant time Ton.

While the present invention has been described in conjunction withpreferred embodiments thereof, it is evident that many alternatives,modifications and variations will be apparent to those skilled in theart. Accordingly, it is intended to embrace all such alternatives,modifications and variations that fall within the spirit and scopethereof as set forth in the appended claims.

What is claimed is:
 1. A frequency jittering control circuit configuredto operably generate a frequency jittering control signal to switch apower switch of a pulse frequency modulation power supply to generate anoutput voltage, the frequency jittering control circuit comprising: apulse frequency modulator connected to the power switch, configured tooperably trigger the control signal responsive to a first signal to turnon the power switch, and configured to operably terminate the controlsignal responsive to a second signal to turn off the power switch; asignal generator configured to operably provide a jittering signalaccording to a count value or a random number; a current detectorconfigured to operably detect a current of the power switch to generatea current sense signal; and a comparator connected to the pulsefrequency modulator, the signal generator and the current detector, andconfigured to operably compare the current sense signal with thejittering signal to generate the second signal.
 2. The frequencyjittering control circuit of claim 1, wherein the signal generatorconfigures to operably adjust a reference signal by a ramp signal togenerate the jittering signal, wherein the ramp signal is adjustableaccording to the count value or the random number.
 3. The frequencyjittering control circuit of claim 1, wherein the signal generatorcomprises: a first voltage-to-current converter configured to operablyconvert a reference voltage into a first current; a first current mirrorconnected to the first voltage-to-current converter, and configured tooperably mirror the first current to generate a second current; a rampgenerator configured to operably generate a ramp signal; a counter or arandom number generator connected to the ramp generator, and configuredto operably generate the count value or the random number to adjust theramp signal; a second voltage-to-current converter connected to the rampgenerator, and configured to operably convert the ramp signal into athird current; a second current mirror connected to the secondvoltage-to-current converter, and configured to operably mirror thethird current to generate a fourth current; and a resistor connected tothe first and second current mirrors, and configured to operablygenerate the jittering signal according to a sum of the second andfourth currents.
 4. The frequency jittering control circuit of claim 1,wherein the signal generator comprises a variable resistor having aresistance adjustable according to the count value or the random number,and the jittering signal is adjusted according to a voltage across thevariable resistor.
 5. The frequency jittering control circuit of claim1, wherein the signal generator comprises: a voltage-to-currentconverter configured to operably convert a reference voltage into afirst current; a current mirror connected to the voltage-to-currentconverter, and configured to operably mirror the first current togenerate a second current; a variable resistor connected to the currentmirror, and configured to operably generate the jittering signalaccording to the second current; and a resistance controller connectedto the variable resistor, and configured to operably adjust a resistanceof the variable resistor according to the count value or the randomnumber to adjust the jittering signal.
 6. The frequency jitteringcontrol circuit of claim 5, wherein the resistance controller comprisesa counter or a random number generator configured to operably generatethe count value or the random number.
 7. The frequency jittering controlcircuit of claim 1, further comprising: an output voltage feedbackcircuit configured to operably detect the output voltage to generate afeedback signal; and a comparator connected to the pulse frequencymodulator and the output voltage feedback circuit, and configured tooperably compare a reference voltage with the feedback signal togenerate the first signal.
 8. A frequency jittering control circuitconfigured to operably generate a frequency jittering control signal toswitch a power switch of a pulse frequency modulation power supply togenerate an output voltage, the frequency jittering control circuitcomprising: an output voltage feedback circuit configured to operablydetect the output voltage to generate a feedback signal; a comparatorconnected to the output voltage feedback circuit, and configured tooperably compare the feedback signal with a reference voltage togenerate a first signal; a one-shot circuit connected to the comparator,and configured to operably be triggered by the first signal to generatea pulse signal; a driver connected to the one-shot circuit, andconfigured to operably generate the control signal responsive to thepulse signal; and a constant time generator connected to the one-shotcircuit, and configured to operably provide a jittering constant timeaccording to a count value or a random number to determine a constant ontime or a non-constant on time of the control signal.
 9. The frequencyjittering control circuit of claim 8, wherein the constant timegenerator comprises: a capacitor; a current source connected to thecapacitor, and configured to operably provide a charging current tocharge the capacitor to generate a charging voltage; and a secondcomparator connected to the capacitor, and configured to operablycompare the charging voltage with a threshold voltage to determine theconstant time; wherein at least one of the capacitor, the chargingcurrent and the threshold voltage is adjusted according to the countvalue or the random number to generate the jittering constant time. 10.A frequency jittering control method for generating a frequencyjittering control signal to switch a power switch of a pulse frequencymodulation power supply to generate an output voltage, the frequencyjittering control method comprising steps of: A.) triggering the controlsignal responsive to a first signal to turn on the power switch; B.)terminating the control signal responsive to a second signal to turn offthe power switch; and C.) jittering the first or second signal to jittera switching frequency of the power switch; wherein the step C comprisessteps of: detecting a current of the power switch to generate a currentsense signal; comparing the current sense signal with a third signal togenerate the second signal; and jittering the third signal according toa count value or a random number.
 11. A frequency jittering controlmethod for generating a frequency jittering control signal to switch apower switch of a pulse frequency modulation power supply to generate anoutput voltage, the frequency jittering control method comprising stepsof: detecting the output voltage to generate a feedback signal;comparing the feedback signal with a reference voltage to generate afirst signal; triggering a pulse signal responsive to the first signal;and jittering a pulse width of the pulse signal according to a countvalue or a random number to jitter a switching frequency of the powerswitch.